Semiconductor device

ABSTRACT

An electrostatic discharge protected transistor of the present invention includes transistors in an active region composed of a p-type semiconductor substrate and surrounded by element isolation regions. On the active region composed of the p-type semiconductor substrate, an on-source silicide film and an on-drain silicide film are provided. The on-drain silicide film is not provided in a portion located on a boundary of each transistor and divided to correspond to the respective transistors. As a result, regions between respective pairs of the transistors have high resistances, and it is, therefore, possible to prevent a current from flowing between the different transistors and prevent local current concentration. It is thereby possible to allow the electrostatic discharge protected transistor to make most use of an electrostatic destruction protection capability per unit area without increasing an area of the transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C §119 on patentapplication Ser. No. 2004-013096 filed in Japan on Jan. 21, 2004, theentire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device. Morespecifically, the present invention relates to an electrostaticdischarge protected transistor.

In recent years, a silicide structure has been widely adopted for asemiconductor device so as to prevent an increase in-parasiticresistance due to a reduction in a thickness of a diffused layerfollowing a scale down of a metal oxide semiconductor (MOS) device.Since the silicide structure has the property of reducing diffusionresistance, the parasitic resistance can be reduced. However, if asilicide film is formed on a plurality of element formation regions, acurrent tends to flow between the adjacent element formation regions.Due to this, if the silicide structure is applied to elements, such aselectrostatic discharge protected transistors, each of which needs tosuddenly carry a high current, in particular, the currentdisadvantageously concentrates on one point and thermal destructioneventually occurs. Therefore, there is proposed a method for preventingcurrent concentration by sub-dividing the electrostatic dischargeprotected transistors into sets (semiconductor moats), and keeping ahigh resistance between the adjacent electrostatic discharge protectedtransistors (see, for example, U.S. Pat. No. 4,825,280).

A conventional electrostatic discharge protected transistor sub-dividedinto sets according to the semiconductor moats will now be describedwith reference to FIGS. 10 and 11A, 11B, and 11C.

FIG. 10 is a plan view which depicts the conventional electrostaticdischarge protected transistor which includes a silicide film. FIGS. 11Ato 11C are sections that depict the conventional electrostatic dischargeprotected transistor. Specifically, FIG. 11A is a section taken along aline A4-A4 of FIG. 10, FIG. 11B is a section taken along a line B4-B4 ofFIG. 10, and FIG. 11C is a section taken along a line C4-C4 of FIG. 10.

As shown in FIG. 10, the conventional electrostatic discharge protectedtransistor is constituted so that a plurality of transistors 121, 122and 123 are arranged to share a common gate electrode among them.

As shown in FIG. 11A, each of the transistors 121 to 123 includeselement isolation regions 102 of a shallow trench isolation (STI)structure each of which has an insulating film buried in a trenchprovided in a p-type semiconductor substrate 101 that consists ofsilicon, a gate insulating film 103 which is provided on an activeregion of the p-type semiconductor substrate 101 and which is composedof a silicon oxide film, a gate electrode 104 which is provided on thegate insulating film 103 and which is composed of a doped polysiliconfilm, and an on-gate silicide film 105 _(G) which is formed on the gateelectrode 104.

Each of the transistors 121 to 123 also includes n-typelow-concentration diffused layers 106 which are formed in regions of theactive region of the semiconductor substrate 101 which regions arelocated below sides of the gate electrode 104, respectively, insulatingsidewall spacers 107 which are formed on side surfaces of the gateelectrode 104, respectively, an n-type high-concentration drain region108 _(D) (108 _(D1), 108 _(D2), or 108 _(D3)) and an n-typehigh-concentration source region 108 _(S) (108 _(S1), 108 _(S2), or 108_(S3)) which are formed in regions of the active region of thesemiconductor substrate 101 which regions are located below respectivesides of the sidewalls 107, an on-drain silicide film 105 _(D) (105_(D1), 105 _(D2), or 105 _(D3)) which is formed on the n-typehigh-concentration drain region 108 _(D), and an on-source silicide film105 _(S) (105 _(S1), 105 _(S2), or 105 _(S3)) which is formed on then-type high-concentration source region 108 _(S).

Further, each transistor includes an interlayer insulating film 109formed on the semiconductor substrate 101, a drain contact 110 _(D) (110_(D1), 110 _(D2), or 110 _(D3)) which penetrates the interlayerinsulating film 109 on the n-type high-concentration drain region 108_(D) and which reaches the on-drain silicide film 105 _(D), a sourcecontact 110 _(S) (110 _(S1), 110 _(S2), or 110 _(S3)) which penetratesthe interlayer insulating film 109 on the n-type high-concentrationsource region 108 _(S) and which reaches the on-source silicide film 105_(S), metal wirings 111 _(D) and 111 _(S) which are formed on theinterlayer insulating film 109 so as to be connected to the draincontact 110 _(D) and the source contact 110 _(S), respectively, and eachof which consists of Al or Al alloy, and an interlayer insulating film112 formed on the interlayer insulating film 109 and the metal wirings111 _(D) and 111 _(S).

With this structure, the on-drain silicide films 105 _(D1), 105 _(D2),and 105 _(D3), the n-type high-concentration drain regions 108 _(D1),108 _(D2), and 108 _(D3), the on-source silicide films 105 _(S1), 105_(S2), and 105 _(S3), and the n-type high-concentration source regions108 _(S1), 108 _(S2), and 108 _(S3) are isolated from one another by theelement isolation regions 102, respectively. The entire electrostaticdischarge protected transistor can, therefore, prevent occurrence oflocal current concentration.

However, according to the conventional art, each of the transistors 121to 123 is sub-divided into sub-transistors corresponding to therespective semiconductor moats. It is, therefore, necessary to provideregions for isolating diffused layers of the respective sub-transistorsfrom one another within each of the transistors 121 to 123. Thisdisadvantageously increases a total area of the electrostatic dischargeprotected transistor.

SUMMARY OF THE INVENTION

It is an object of the present invention to prevent local currentconcentration without increasing an area of an integrated circuitincluding salicide transistors.

According to one aspect of the present invention, there is provided afirst semiconductor device, comprising: a semiconductor substrate whichincludes an active region; an element isolation region provided in aregion surrounding sides of the active region of the semiconductorsubstrate; a gate insulating film provided on the active region; a gateelectrode provided on the gate insulating film; a source region and adrain region which are provided in regions located below sides of thegate electrode in the active region, respectively; an on-source silicidefilm provided on the source region; an on-drain silicide film providedon the drain region; a plurality of source contacts which are providedover the source region with the on-source silicide film interposedtherebetween, and which are aligned in a gate width direction; and aplurality of drain contacts which are provided over the drain regionwith the on-drain silicide film interposed therebetween, and which arealigned in the gate width direction, wherein the on-drain silicide filmis provided to be divided into a plurality of on-drain silicide filmsand the resultant on-drain silicide films are isolated from one anotherin at least one region out of regions located between respectiveadjacent pairs of the drain contacts among the plurality of draincontacts.

By so constituting, the region in which the on-drain silicide films arenot provided has a high resistance. Therefore, it is possible to preventa current flowing between one drain contact and one source contact fromflowing between the other drain contact and the other source contact foradjacent drain contacts. Thus, local current concentration can beprevented without causing an increase in the area of the semiconductordevice.

It is preferable that the on-drain silicide film is provided to bedivided into segments and the resultant divided on-drain silicide filmsare isolated to correspond to the drain contacts, respectively. If so,the on-drain suicide films are provided to be isolated from one anotherto correspond to the respective drain contacts, thereby making itpossible to ensure preventing the current from flowing between theelements.

The on-source silicide film may be provided on an entire surface of thesource region.

Needless to say, however, if the on-source silicide film is divided intoa plurality of on-source silicide films and the resultant on-sourcesilicide films are isolated from one another in at least one region outof regions located between respective adjacent pairs of the sourcecontacts among the plurality of source contacts, it is possible tofurther ensure preventing the current concentration.

As a specific structure for isolating the on-drain silicide films fromone another, there is a structure in which a protection film is providedon the drain region in at least one region out of regions put betweenthe respective adjacent pairs of the drain contacts among the pluralityof drain contacts, thereby providing the on-drain silicide films to beisolated from one another.

The gate electrode may be composed of a polysilicon film, and an on-gatesilicide film may be formed on the gate electrode.

According to another aspect of the present invention, there is provideda second semiconductor device, comprising: a semiconductor substratewhich includes an active region; an element isolation region provided ina region surrounding sides of the active region of the semiconductorsubstrate; a gate insulating film provided on the active region; a gateelectrode provided on the gate insulating film; a source region and adrain region which are provided in regions located below sides of thegate electrode in the active region, respectively; an on-source silicidefilm provided on the source region; an on-drain silicide film providedon the drain region; a plurality of source contacts which are providedover the source region with the on-source silicide film interposedtherebetween, and which are aligned in a gate width direction; and aplurality of drain contacts which are provided over the drain regionwith the on-drain silicide film interposed therebetween, and which arealigned in the gate width direction, wherein the on-drain silicide filmincludes a narrow-width silicide region in at least one region out ofregions located between respective adjacent pairs of the drain contactsamong the plurality of drain contacts, the narrow-width silicide regionbeing smaller in a width in a gate length direction than respectiveregions where the drain contacts are formed.

By so constituting, the narrow-width silicide film has a highresistance. Therefore, it is possible to prevent a current flowingbetween the drain contact and the source contact of one element fromflowing between the drain contact and the source contact of the otherelement. Thus, local current concentration can be prevented withoutcausing an increase in the area of the semiconductor device.

It is preferable that the narrow-width silicide region is provided ineach of the regions located between the respective adjacent pairs of thedrain contacts among the plurality of drain contacts. If so, on-drainsilicide films are provided to be isolated from one another tocorrespond to respective elements. It is, therefore, possible to ensurepreventing a current from flowing between the elements.

As a specific structure for providing the narrow-width silicide film,there is a structure in which a dummy gate insulating film and a dummygate electrode located on the dummy gate insulating film are provided onthe at least one region out of the regions located between therespective adjacent pairs of the drain contacts among the plurality ofdrain contacts, and in which the narrow-width silicide region isprovided on the drain region located between the dummy gate electrodeand the gate electrode. With this structure, the dummy gate insulatingfilm and the dummy gate electrode can be formed to have a smaller planearea than that of the conventional element isolation region. It is,therefore, possible to prevent an increase in the area of thesemiconductor device. Further, since the gat electrode and the gatecapacitance are provided to be isolated from each other, the gatecapacitance is not increased.

As another specific structure for providing the narrow-width silicidefilm, there is a structure in which a protection film is provided on theat least one region out of the regions located between the respectiveadjacent pairs of the drain contacts among the plurality of draincontacts on the train region, and in which the narrow-width silicideregion is provided on the drain region located between the protectionfilm and the gate electrode. With this structure, the on-drain silicidefilm on the adjacent drain regions can be set to have a high resistancewithout isolating the adjacent drain regions from each other. Therefore,it is possible to secure the drain region that functions as the activeregion, and thereby prevent an increase in the area of the semiconductordevice.

A width of the drain region in the gate length direction in the at leastone region in which the narrow-width silicide region is formed may beequal to a width of the drain region in the gate length direction in theregions in which the drain contacts are formed.

Further, in the second semiconductor device according to the presentinvention, similarly to the first semiconductor device, the on-sourcesilicide film may include a narrow-width silicide region in at least oneregion out of regions located between respective adjacent pairs of thesource contacts among the plurality of source contacts, the narrow-widthsilicide region being smaller in a width in a gate length direction thanrespective regions where the source contacts are formed. If so, it ispossible to further ensure preventing the current concentration.

As a specific structure for providing the source-side narrow-widthsilicide region, there is a structure in which a dummy gate insulatingfilm and a dummy gate electrode located on the dummy gate insulatingfilm are provided on the at least one region out of the regions locatedbetween the respective adjacent pairs of the source contacts among theplurality of source contacts on the source region, and in which thesource-side narrow-width silicide film is provided on the source regionlocated between the dummy gate electrode and the gate electrode.

As another specific structure for providing the source-side narrow-widthsilicide film, there is a structure in which a source-side protectionfilm is provided on the at least one region out of the regions locatedbetween the respective adjacent pairs of the source contacts among theplurality of source contacts on the source region, and in which thesource-side narrow-width silicide region is provided on the sourceregion located between the source-side protection film and the gateelectrode.

A width of the source region in the gate length direction in the atleast one region in which the source-side narrow-width silicide regionis formed may be equal to a width of the source region in the gatelength direction in the regions in which the source contacts are formed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view which depicts an electrostatic discharge protectedtransistor according to a first embodiment of the present invention.

FIGS. 2A to 2C are sections which depict the electrostatic dischargeprotected transistor according to the first embodiment of the presentinvention, wherein FIG. 2A is a section taken along a line A1-A1 of FIG.1, FIG. 2B is a section taken along a line B1-B1 of FIG. 1, and FIG. 2Cis a section taken along a line C1-C1 of FIG. 1.

FIG. 3 is a plan view which depicts a modification of the electrostaticdischarge protected transistor according to the first embodiment of thepresent invention.

FIG. 4 is a plan view which depicts a electrostatic discharge protectedtransistor according to a second embodiment of the present invention.

FIGS. 5A to 5C are sections which depict the electrostatic dischargeprotected transistor according to the second embodiment of the presentinvention, wherein FIG. 5A is a section taken along a line A2-A2 of FIG.4, FIG. 5B is a section taken along a line B2-B2 of FIG. 4, and FIG. 5Cis a section taken along a line C2-C2 of FIG. 4.

FIG. 6 is a plan view which depicts a modification of the electrostaticdischarge protected transistor according to the second embodiment of thepresent invention.

FIG. 7 is a plan view which depicts an electrostatic discharge protectedtransistor according to a third embodiment of the present invention.

FIGS. 8A to 8C are sections which depict the electrostatic dischargeprotected transistor according to the first embodiment of the presentinvention, wherein FIG. 8A is a section taken along a line A3-A3 of FIG.7, FIG. 8B is a section taken along a line B3-B3 of FIG. 7, and FIG. 8Cis a section taken along a line C3-C3 of FIG. 7.

FIG. 9 is a plan view which depicts a modification of the electrostaticdischarge protected transistor according to the second embodiment of thepresent invention.

FIG. 10 is a plan view which depicts a conventional electrostaticdischarge protected transistor including a silicide film.

FIGS. 11A to 11C are sections which depict the conventionalelectrostatic discharge protected transistor, wherein FIG. 11A is asection taken along a line A4-A4 of FIG. 10, FIG. 11B is a section takenalong a line B4-B4 of FIG. 10, and FIG. 11C is a section taken along aline C4-C4 of FIG. 10.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, preferred embodiments of the present invention will bedescribed with reference to the accompanying drawings, in which the samereference numerals denote the same components, respectively.

First Embodiment

A structure of an electrostatic discharge protected transistor accordingto a first embodiment of the present invention will be described withreference to FIG. 1 and FIGS. 2A to 2C.

FIG. 1 is a plan view which depicts an electrostatic discharge protectedtransistor according to the first embodiment of the present invention.FIGS. 2A to 2C are sections which depict the electrostatic dischargeprotected transistor according to the first embodiment of the presentinvention. Specifically, FIG. 2A is a section taken along a line A1-A1of FIG. 1, FIG. 2B is a section taken along a line B1-B1 of FIG. 1, andFIG. 2C is a section taken along a line C1-C1 of FIG. 1.

As shown in FIG. 1, the electrostatic discharge protected transistoraccording to the first embodiment is constituted so that a plurality oftransistors, i.e., transistors 21, 22, and 23 are arranged to share acommon electrode 4 among them.

As shown in FIG. 2A, each of the transistors 21 to 23 includes anelement isolation region 2 of an STI structure which has an insulatingfilm buried in a trench provided in a p-type semiconductor substrate 1that consists of silicon, a gate insulating film 3 which is provided onan active region of the p-type semiconductor substrate 1 and which iscomposed of a silicon oxide film, a gate electrode 4 which is providedon the gate insulating film 3 and which is composed of a dopedpolysilicon film, and an on-gate silicide film 5G which is formed on thegate electrode 4.

Each of the transistors 21 to 23 also includes n-type low-concentrationdiffused layers 6 which are formed in regions of the active region ofthe semiconductor substrate 1 which regions are located below respectivesides of the gate electrode 4, insulating sidewall spacers 7 which areformed on respective side surfaces of the gate electrode 4, an n-typehigh-concentration drain region 8 _(D) and an n-type high-concentrationsource region 8 _(S) which are formed in regions of the active region ofthe semiconductor substrate 1 which regions are located below respectivesides of the sidewalls 7, an on-drain silicide film 5 _(D) (5 _(D1), 5_(D2), or 5 _(D3)) which is formed on the n-type high-concentrationdrain region 8 _(D), and an on-source silicide film 5 _(S) which isformed on the n-type high-concentration source region 8 _(S). Theon-gate silicide film 5 _(G), the on-drain silicide film 5 _(D), and theon-source silicide film 5 _(S) are composed of cobalt silicide films,respectively, and are formed simultaneously by a salicide technique.

Further, each transistor includes an interlayer insulating film 9 formedon the semiconductor substrate 1, a drain contact 10 _(D) (10 _(D1), 10_(D2), or 10 _(D3)) which penetrates the interlayer insulating film 9 onthe n-type high-concentration drain region 8 _(D) and which reaches theon-drain silicide film 5 _(D), a source contact 10 _(S) (10 _(S1), 10_(S2), or 10S3) which penetrates the interlayer insulating film 9 on then-type high-concentration source region 8 _(S) and which reaches theon-source silicide film 5 _(S), metal wirings 11 _(D) and 11 _(S) whichare formed on the interlayer insulating film 9 so as to be connected tothe- drain contact 10 _(D) and the source contact 10 _(S), respectively,and each of which consists of Al or Al alloy, and an interlayerinsulating film 12 formed on the interlayer insulating film 9 and themetal wirings 11 _(D) and 11 _(S). The metal wirings 11 _(D) and 11 _(S)may be formed by a so-called single damascene method for forming each ofthe metal wirings 11 _(D) and 11 _(S) by forming a contact hole and awiring groove in an interlayer insulating film and then burying a Cufilm.

A first feature of the first embodiment is in that the element isolationregion 2 is not provided in a region located on a boundary of each ofthe transistors 21 to 23, as shown in FIGS. 2B and 2C. Namely, theactive regions of the transistors 21 to 23 are isolated from anotherregion by the element isolation regions 2 but the transistors 21 to 23are not isolated from one another.

A second feature of the first embodiment is in that the on-drainsilicide films 5 _(D1), 5 _(D2), and 5 _(D3) are provided on the n-typehigh-concentration drain region 8 _(D) to be divided by regions 13 _(D)to correspond to the respective transistors 21 to 23 as shown in FIG. 1and FIGS. 2A to 2C. In addition, the on-source silicide film 5 _(S) isformed on an entire surface of the n-type high-concentration sourceregion 8 _(S).

In this embodiment, since the on-drain silicide films 5 _(D1), 5 _(D2),and 5 _(D3) are provided to correspond to the respective transistors 21to 23 on the n-type high-concentration drain region 8 _(D), a resistanceof the region 13 _(D) between the adjacent drain regions is high. Thiscan prevent a current from flowing between the adjacent transistors,e.g., prevent a current flowing between the drain contact 10 _(D1) andthe source contact 10 _(S1) from flowing between the drain contact 10_(D2) and the source contact 10 _(S2). Accordingly, the transistors 21to 23 are not isolated from one another by the element isolation regions2, SO that local curtent concentration can be prevented withoutincreasing an area of the electrostatic discharge protected transistor.Since a drain region is higher in electric field than a source region,current concentration tends to occur to the drain region more frequentlythan the source region. For this reason, the on-drain silicide films 5_(D) (5 _(D1), 5 _(D2), and 5 _(D3)) are formed for the respectivetransistors 21 to 23, and the common on-source silicide film 5 _(S) isprovided to be shared among the transistors 21 to 23.

A method for manufacturing the semiconductor device according to thisembodiment will next be described briefly.

First, the element isolation region 2, the gate insulating film 3, thegate electrode 4, and the n-type low-concentration diffused layers 6 areformed using a well-known technique. An oxide film having a thickness of50 nm for formation of a sidewall is then formed on the substrate 1, andn-type impurities such as arsenic (As) or phosphorus (P) are doped byion implantation, thereby forming the n-type high-concentration drainregion 8 _(D) and the n-type high-concentration source region 8 _(S).

Using photolithography and dry etching technique, the oxide film isselectively etched, thereby forming the sidewall spacers 7 on therespective side surfaces of the gate electrode 4. At the same time, aprotection film (not shown) composed of an oxide film is formed on apart (each region 13 _(D)) on the high-concentration drain region 8_(D). This protection film is formed in a region between the adjacentdrain contacts 10 _(D), to be formed at a later step, so as to cross then-type high-concentration drain region 8 _(D) in a gate lengthdirection.

After forming a cobalt film on the entire surface of the substrate 1, afirst heat treatment is performed for siliciding the cobalt film,thereby forming the on-gate silicide film 5 _(G) on the gate electrode4, the on-drain silicide films 5 _(D) (5 _(D1), 5 _(D2), and 5 _(D3)) onthe n-type high-concentration drain region 8 _(D), and the on-sourcesilicide film 5 _(S) on the n-type high-concentration source region 8_(S). At this time, the cobalt silicide film is not formed on theprotection film formed on the region 13 _(D) in the n-typehigh-concentration drain region 8 _(D). Therefore, the on-drain silicidefilm 5 _(D) is formed to be divided to the three on-drain silicide films5 _(D1), 5 _(D2), and 5 _(D3).

After selectively removing the unreacted cobalt film, a second heattreatment is performed to thereby stabilize structures of the silicidefilms 5 _(G), 5 _(S), and 5 _(D). The protection film is then removed.

After forming the interlayer insulating film 9 on the substrate 1, aplurality of contact holes are formed in the interlayer insulating film9, and a conductive material is buried into each contact hole, therebyforming the drain contact 10 _(D1), 10 _(D2), 10 _(D3), and the sourcecontacts 10 _(S1), 10 _(S2), and 10 _(S3). Next, after forming the metalwirings 11 _(D) and 11 _(S) connected to the drain contacts 10 _(D1), 10_(D2), and 10 _(D3), and to the source contacts 10 _(S1), 10 _(S2), and10 _(S3) on the interlayer insulating film 9, respectively, theinterlayer insulating film 12 is formed. The semiconductor deviceaccording to this embodiment can be thereby obtained.

Alternatively, the protection film for preventing the silicide film frombeing formed on the region 13 _(D) may be left without removing it. Ifso, with the structure shown in FIGS. 1, 2B, and 2C, the protection filmremains present -between the n-type high-concentration drain region 8_(D) and the interlayer insulating film 9 in the region 13 _(D) which islocated on the n-type high-concentration drain region 8 _(D) and onwhich the silicide film is not formed.

Modification of First Embodiment

A modification of the first embodiment will be described with referenceto FIG. 3. FIG. 3 is a plan view which depicts a modification of theelectrostatic discharge protected transistor according to the firstembodiment of the present invention. In FIG. 3, the same referencenumerals denote the same constituent elements as those in the firstembodiment shown in FIG. 1.

In this modification, the on-source silicide film 5 _(S) on the n-typeconcentration source region 8 _(S) is divided to the three silicidefilms 5 _(S1), 5 _(S2), and 5 _(S3) to correspond to the respectivetransistors 21 to 23. The other constituent elements are equal to thoseshown in FIG. 1.

In this modification, since the on-source silicide films 5 _(S1), 5_(S2), and 5 _(S3) are isolated from one another by the regions 13 _(S),adjacent source contacts 10 _(S1), 10 _(S2), and 10 _(S3) are notelectrically connected to one another by the silicide film.

With this configuration, the same advantages as those of the firstembodiment can be attained. In addition, since the on-source suicidefilms 5 _(S1), 5 _(S2), and 5 _(S3) are isolated from one another tocorrespond to the respective elements, it is possible to further ensurepreventing the local current concentration. Namely, since the regions 13_(D) between the respective pairs of the adjacent drains and the regions13 _(S) between the respective pairs of the adjacent sources have highresistances, it is possible to prevent a current from flowing betweenthe adjacent transistors, e.g., prevent a current flowing between thedrain contact 10 _(D1) and the source contact 10 _(S1) from flowingbetween the drain contact 10 _(D2) and the source contact 10 _(S2). As aconsequence and because of the fact that the transistors 21 to 23 arenot isolated from one another by the element isolation regions, it ispossible to prevent the local current concentration without causing anincrease in the area of the semiconductor device.

Second Embodiment

A structure of an electrostatic discharge protected transistor accordingto a second embodiment of the present invention will be described withreference to FIG. 4 and FIGS. 5A to 5C.

FIG. 4 is a plan view which depicts an electrostatic discharge protectedtransistor according to the second embodiment of the present invention.FIGS. 5A to 5C are sections which depict the electrostatic dischargeprotected transistor according to the second embodiment of the presentinvention. Specifically, FIG. 5A is a section taken along a line A2-A2of FIG. 4, FIG. 5B is a section taken along a line B2-B2 of FIG. 1, andFIG. 5C is a section taken along a line C2-C2 of FIG. 5.

As shown in FIG. 4, the electrostatic discharge protected transistoraccording to the second embodiment is constituted so that a plurality oftransistors, i.e., transistors 21, 22, and 23 are arranged to share acommon electrode 4 among them.

As shown in FIG. 5A, each of the transistors 21 to 23 includes anelement isolation region 2 of an STI structure which has an insulatingfilm buried in a trench formed in a p-type semiconductor substrate 1that consists of silicon, a gate insulating film 3 which is provided onan active region of the p-type semiconductor substrate 1 and which iscomposed of a silicon oxide film, a gate electrode 4 which is providedon the gate insulating film 3 and which is composed of a dopedpolysilicon film, and an on-gate silicide film 5 _(G) which is providedon the gate electrode 4.

Each of the transistors 21 to 23 also includes n-type low-concentrationdiffused layers 6 which are formed in regions of the active region ofthe semiconductor substrate 1 which regions are located below respectivesides of the gate electrode 4, insulating sidewall spacers 7 which areformed on respective side surfaces of the gate electrode 4, an n-typehigh-concentration drain region 8 _(D) and an n-type high-concentrationsource region 8 _(S) which are formed in regions of the active region ofthe semiconductor substrate 1 which regions are located below respectivesides of the sidewalls 7, an on-drain silicide film 5 _(D) which isformed on the n-type high-concentration drain region 8 _(D), and anon-source silicide film 5 _(S) which is formed on the n-typehigh-concentration source region 8 _(S). The on-gate silicide film 5_(G), the on-drain silicide film 5 _(D), and the on-source silicide film5 _(S) are composed of cobalt silicide films, respectively, and areformed simultaneously by a salicide technique.

Further, each transistor includes an interlayer insulating film 9 formedon the semiconductor substrate 1, a drain contact 10 _(D) (10 _(D1), 10_(D2), or 10 _(D3)) which penetrates the interlayer insulating film 9 onthe n-type high-concentration drain region 8 _(D) and which reaches theon-drain silicide film 5 _(D), a source contact 10 _(S) (10 _(S1), 10_(S2), or 10 _(S3)) which penetrates the interlayer insulating film 9 onthe n-type high-concentration source region 8 _(S) and which reaches theon-source silicide film 5 _(S), metal wirings 11 _(D) and 11 _(S) whichare formed on the interlayer insulating film 9 so as to be connected tothe drain contact 10 _(D) and the source contact 10 _(S), respectively,and each of which consists of Al or Al alloy, and an interlayerinsulating film 12 formed on the interlayer insulating film 9 and themetal wirings 11 _(D) and 11 _(S). The metal wirings 11 _(D) and 11 _(S)may be formed by a so-called single damascene method for forming each ofthe metal wirings 11 _(D) and 11 _(S) by forming a contact hole and awiring groove in an interlayer insulating film and then burying a Cufilm.

A feature of the second embodiment is in that a dummy gate insulatingfilm 3 _(X), a dummy gate electrode 4 _(X) located on the dummy gateinsulating film 3 _(X) and composed of a doped polysilicon film, anon-dummy-gate silicide film 5 _(GX) located on the dummy gate electrode4 _(X), and dummy sidewall spacers 7 _(X) located on side surfaces ofthe dummy gate electrode 4 _(X) are provided on regions located betweenrespective adjacent pairs of the drain contacts 10 _(D1) to 10 _(D3) inthe n-type high-concentration drain region 8 _(D), as shown in FIG. 4and FIGS. 5B and 5C. The dummy gate insulating film 3 _(X), the dummygate electrode 4 _(X), the on-dummy-gate silicide film 5 _(GX), and thedummy sidewall spacers 7 _(X) are formed simultaneously using the samematerials as those for the corresponding gate insulating film 3, gateelectrode 4, the on-gate silicide film 5 _(G), and the sidewall spacers7, respectively.

As shown in FIG. 4 and FIGS. 5A and 5B, the on-source silicide film 5_(S) is formed on an entire surface of the n-type high-concentrationsource region 8 _(S), and a plurality of source contacts 10 _(S1), 10_(S2), and 10 _(S3) formed on the n-type high-concentration sourceregion 8 _(S) are electrically connected to one another by alow-resistance on-source silicide film 5 _(S).

The dummy gate electrode 4 _(X) is arranged to be isolated from the gateelectrode 4. By providing the dummy gate electrode 4 _(X), a width of anon-drain silicide film 5 _(DX) between the dummy gate electrode 4 _(X)and the gate electrode 4 is smaller than that of the on-drain silicidefilm 5 _(D) in other portions thereof. If the width of the silicide filmis smaller, a sheet resistance is higher. Due to this, the on-drainsilicide film 5 _(DX) does not function as a low-resistance layer. If acobalt silicide film is formed, for example, and if the width of theon-drain silicide film 5 _(DX) in the gate length direction is as smallas 0.1 μm or less, the sheet resistance is conspicuously increased.

Thus, the region between the drain contacts 10 _(D1) and 10 _(D2) andthat between the drain contacts 10 _(D2) and 10 _(D3) are constituted tobe connected to each other by the high-resistance on-drain silicide film5 _(DX). Therefore, it is possible to prevent a current from flowingbetween the adjacent transistors, e.g., prevent a current flowingbetween the drain contact 10 _(D1) and the source contact 10 _(S1) fromflowing between the drain contact 10 _(D2) and the source contact 10_(S2). It is thus possible to prevent local current concentration. It isnoted that the semiconductor device can be formed to have a smallerplane area when the dummy gate electrode 4 _(X) as described in thisembodiment is provided than that when the element isolation is employedas described in the section of BACKGROUND OF THE INVENTION. Therefore,it is possible to more greatly prevent an increase in the area of thesemiconductor according to this embodiment. Further, this embodiment hasthe following advantage. Since the gate electrode 4 is isolated from thedummy gate electrode 4 _(X), a gate capacitance is not increased.

The sidewall spacers 7 and 7 _(X) are formed on the side surfaces of thegate electrode 4 and the dummy gate electrode 4 _(X), respectively.Therefore, by setting a distance between the gate electrode 4 and thedummy gate electrode 4 _(X) to be more than double the width of each ofthe sidewall spacers 7 and 7 _(X), the silicide film can be formedbetween the gate electrode 4 and the dummy gate electrode 4 _(X).

A method for manufacturing the semiconductor device according to thisembodiment will next be described briefly.

First, the element isolation region 2 is formed by removing a part ofthe semiconductor substrate 1 and burying an insulating film. The gateinsulating film 3 and the gate electrode 4 are then formed on the activeregion of the semiconductor substrate 1. At the same time, the dummygate insulating film 3 _(X) and the dummy gate electrode 4 _(X) areformed n a drain formation region. At this moment, the dummy gateinsulating film 3 _(X) and the dummy gate electrode 4 _(X) are formed onthe regions located between the respective adjacent pairs of the draincontacts 10 _(D1) to 10 _(D3) (shown in FIG. 4) so as to be distancedfrom the gate electrode 4. Thereafter, n-type impurities are doped byion implantation while using the gate electrode 4 and the dummyelectrode 4 _(X) as a mask, thereby forming the n-type low-concentrationdiffused layer 6.

An oxide film having a thickness of 50 μm for formation of a sidewall isformed on the substrate 1, and the oxide film is then subjected to dryetching, thereby forming the sidewall spacers 7 and 7 _(X) on therespective side surfaces of the gate electrode 4 and the dummy gateelectrode 4 _(X). Thereafter, n-type impurities are doped by ionimplantation while using the gate electrode 4, the dummy gate electrode4 _(X), and the sidewall spacers 7 and 7 _(X) as a mask, thereby formingthe n-type high-concentration drain region 8 _(D) and the n-typehigh-concentration source region 8 _(S).

After forming a cobalt film on the entire surface of the substrate 1, afirst heat treatment is performed for siliciding the cobalt film,thereby forming the on-gate silicide film 5 _(G) on the gate electrode4, the on-dummy-gate silicide film 5 _(GX) on the dummy gate electrode 4_(X), the on-drain silicide film 5 _(D) on the n-type high-concentrationdrain region 8 _(D), and the on-source silicide film 5 _(S) on then-type high-concentration source region 8 _(S).

At this time, in the region located between the dummy gate electrode 4_(X) and the gate electrode 4 in the n-type high-concentration drainregion 8 _(D), the high-resistance on-drain silicide film 5 _(DX)smaller in the width in the gate length direction than that of theon-drain silicide film 5 in other portions thereof is formed. Afterselectively removing the unreacted cobalt film, a second heat treatmentis performed to thereby stabilize structures of the respective silicidefilms 5 _(G), 5 _(GX), 5 _(S), and 5 _(D). Thereafter, the interlayerinsulating film 9 is formed on the substrate 1, a plurality of contactholes are formed in the interlayer insulating film 9, and a conductivematerial is buried into each contact hole, thereby forming the draincontact 10 _(D1), 10 _(D2), 10 _(D3), and the source contacts 10 _(S1),10 _(S2), and 10 _(S3) (shown in FIG. 4). Next, after forming the metalwirings 11 _(D) and 11 _(S) is connected to the drain contacts 10 _(D1),10 _(D2), and 10 _(D3), and to the source contacts 10 _(S1), 10 _(S2),and 10 _(S3) on the interlayer insulating film 9, respectively, theinterlayer insulating film 12 is formed. The semiconductor deviceaccording to this embodiment can be thereby obtained.

Modification of Second Embodiment

A modification of the second embodiment will be described with referenceto FIG. 6. FIG. 6 is a plan view which depicts a modification of theelectrostatic discharge protected transistor according to the secondembodiment of the present invention. In FIG. 6, the same referencenumerals denote the same constituent elements as those in the secondembodiment shown in FIG. 4.

In this modification, a dummy gate insulating film (not shown), a dummygate electrode (not shown), the on-dummy-gate silicide film 5 _(GX), andthe dummy sidewall spacers 7 _(X) are provided also on the n-typehigh-concentration source region 8 _(S). Namely, the dummy gateinsulating film, the dummy gate electrode formed on the dummy gateinsulating film, the on-dummy-gate silicide film 5 _(GX) formed on thedummy gate electrode, and the dummy sidewall spacers 7 _(X) formed onside surfaces of the dummy gate electrode are provided on regionslocated between respective adjacent pairs of the source contacts 10_(S1) to 10 _(S3) on the n-type high-concentration source region 8 _(S).In addition, an on-source silicide film 5 _(SX) smaller in width in thegate length direction than the on-source silicide film 5 _(SX) in otherregions is fonned in portions located between the dummy gate electrode 4_(X) and the gate electrode 4 on the n-type high-concentration sourceregion 8 _(S). The other constituent elements are equal to those shownin FIG. 4.

With this configuration, the same advantages as those of the secondembodiment can be attained. In addition, since the small-width andhigh-resistance on-source silicide film 5 _(SX) is provided between therespective pairs of the transistors 21 to 23, it is possible to furtherensure preventing the local current concentration. Namely, since theregions between the respective pairs of the adjacent drains and theregions between the respective pairs of the adjacent sources have highresistances, it is possible to prevent a current from flowing betweenthe adjacent transistors, i.e., prevent a current flowing between thedrain contact 10 _(D1) and the source contact 10 _(S1) from flowingbetween the drain contact 10 _(D2) and the source contact 10 _(S2). As aconsequence and because of the fact that the transistors 21 to 23 arenot isolated from one another by the element isolation regions, it ispossible to prevent the local current concentration without causing anincrease in the area of the semiconductor device.

Third Embodiment

A structure of an electrostatic discharge protected transistor accordingto a third embodiment of the present invention will be described withreference to FIG. 7 and FIGS. 8A to 8C.

FIG. 7 is a plan view which depicts an electrostatic discharge protectedtransistor according to the third embodiment of the present invention.FIGS. 8A to 8C are sections which depict the electrostatic dischargeprotected transistor according to the third embodiment of the presentinvention. Specifically, FIG. 8A is a section taken along a line A3-A3of FIG. 7, FIG. 8B is a section taken along a line B3-B3 of FIG. 7, andFIG. 8C is a section taken along a line C3-C3 of FIG. 7.

As shown in FIG. 7, the electrostatic discharge protected transistoraccording to the third embodiment is constituted so that that aplurality of transistors, i.e., transistors 21, 22, and 23 are arrangedto share a common electrode 4 among them.

As shown in FIG. 8A, each of the transistors 21 to 23 includes anelement isolation region 2 of an STI structure which has an insulatingfilm buried in a trench provided in a p-type semiconductor substrate 1that consists of silicon, a gate insulating film 3 which is provided onan active region of the p-type semiconductor substrate 1 and which iscomposed of a silicon oxide film, a gate electrode 4 which is providedon the gate insulating film 3 and which is composed of a dopedpolysilicon film, and an on-gate silicide film 5 _(G) which is formed onthe gate electrode 4.

Each of the transistors 21 to 23 also includes n-type low-concentrationdiffused layers 6 which are formed in regions of the active region ofthe semiconductor substrate 1 which regions are located below respectivesides of the gate electrode 4, insulating sidewall spacers 7 which areformed on respective side surfaces of the gate electrode 4, an n-typehigh-concentration drain region 14 _(D) and an n-type high-concentrationsource region 14 _(S) which are formed in regions of the active regionof the semiconductor substrate 1 which regions are located belowrespective sides of the sidewall spacers 7, an on-drain silicide film 5_(D) which is formed on the n-type high-concentration drain region 14_(D), and an on-source silicide film 5 _(S) which is formed on then-type high-concentration source region 14 _(S). The on-gate silicidefilm 5 _(G), the on-drain silicide film 5 _(D), and the on-sourcesilicide film 5 _(S) are composed of cobalt silicide films,respectively, and are formed simultaneously by a salicide technique.

Further, each transistor includes an interlayer insulating film 9 formedon the semiconductor substrate 1, a drain contact 10 _(D) (10 _(D1), 10_(D2), or 10 _(D3)) which penetrates the interlayer insulating film 9 onthe n-type high-concentration drain region 14 _(D) and which reaches theon-drain silicide film 5 _(D), a source contact 10 _(S) (10 _(S1), 10_(S2), or 10 _(S3)) which penetrates the interlayer insulating film 9 onthe n-type high-concentration source region 14 _(S) and which reachesthe on-source silicide film 5 _(S), metal wirings 11 _(D) and 11 _(S)which are formed on the interlayer insulating film 9 so as to beconnected to the drain contact 10 _(D) and the source contact 10 _(S),respectively, and each of which consists of Al or Al alloy, and aninterlayer insulating film 12 formed on the interlayer insulating film 9and the metal wirings 11 _(D) and 11 _(S). The metal wirings 11 _(D) and11 _(S) may be formed by a so-called single damascene method for formingeach of the metal wirings 11 _(D) and 11 _(S) by forming a contact holeand a wiring groove in an interlayer insulating film and then burying aCu film.

A first feature of the third embodiment is in that the element isolationregion 2 is not provided in a region located on a boundary of each ofthe transistors 21 to 23, as shown in FIGS. 8B and 8C. Namely, theactive regions of the transistors 21 to 23 are isolated from anotherregion by the element isolation regions 2 but the transistors 21 to 23are not isolated from one another.

A second feature of the third embodiment is in that regions 13 _(D) inwhich the silicide film is not formed are provided in part of regionslocated between respective pairs of the drain contacts 10 _(D1) to 10_(D3) in the n-type high-concentration drain region 14 _(D), as shown inFIG. 7 and FIG. 8B. In addition, the on-source silicide film 5 _(S) isformed on an entire surface of the n-type high-concentration sourceregion 14 _(S).

In this embodiment, a width of an on-drain silicide film 5 _(DX) locatedbetween the respective pairs of the drain contacts 10 _(D1) to 10 _(D3)out of the on-drain silicide film 5 _(D) is smaller in a gate lengthdirection than a width of the on-drain silicide film 5 _(D) in otherregions thereof. If the width of the silicide film is smaller, a sheetresistance is higher. Due to this, the on-drain silicide film 5 _(DX)does not function as a low-resistance layer. Thus, the region betweenthe drain contacts 10 _(D1) and 10 _(D2) and that between the draincontacts 10 _(D2) and 10 _(D3) are constituted to be connected to eachother by the high-resistance on-drain silicide film 5 _(DX). Therefore,it is possible to prevent a current from flowing between the adjacenttransistors, e.g., prevent a current flowing between the drain contact10 _(D1) and the source contact 10 _(S1) from flowing between the draincontact 10 _(D2) and the source contact 10 _(S2). As a consequence andbecause of the fact that the transistors 21 to 23 are not isolated fromone another by the element isolation regions 2, it is possible toprevent the local current concentration without causing an increase inthe area of the semiconductor device. Since a drain region is higher inelectric field than a source region, current concentration tends tooccur to the drain region more frequently than the source region. Forthis reason, the on-drain silicide films 5 _(DX) having the narrow widthof the silicide film is formed only in the n-type high-concentrationdrain region 14 _(D), and the on-source silicide film 5 _(S) is formedon the entire surface of the n-type high-concentration source region 14_(S).

A method for manufacturing the semiconductor device according to thisembodiment will next be described briefly.

First, the element isolation region 2, the gate insulating film 3, thegate electrode 4, and the n-type low-concentration diffused layers 6 areformed using a well-known technique. An oxide film having a thickness of50 nm for formation of a sidewall is then formed on the substrate 1, andn-type impurities such as arsenic (As) or phosphorus (P) are doped byion implantation, thereby forming the n-type high-concentration drainregion 14 _(D) and the n-type high-concentration source region 14 _(S).

Using photolithography and dry etching technique, the oxide film isselectively etched, thereby forming the sidewall spacers 7 on therespective side surfaces of the gate electrode 4. At the same time, aprotection film (not shown) composed of an oxide film is formed on apart (each region 13 _(D)) on the high-concentration drain region 14_(D) between the respective pairs of adjacent drain contacts formed at alater step. In this embodiment, the protection film is formed to bespaced apart from the sidewall spacers 7 formed on the respective sidesurfaces of the gate electrode 7.

After forming a cobalt film on the entire surface of the substrate 1, afirst heat treatment is performed for siliciding the cobalt film,thereby forming the on-gate silicide film 5 _(G) on the gate electrode4, the on-drain silicide film 5 _(D) on the n-type high-concentrationdrain region 14 _(D), and the on-source silicide film 5 _(S) on then-type high-concentration source region 14 _(S). At this time, thecobalt silicide film is not formed on the protection film formed on theregion 13 _(D). Therefore, the high-resistance on-drain silicide film 5_(DX) smaller in width in the gate length direction than the on-drainsilicide film 5 _(D) in other regions is formed in the region locatedbetween the region 13 _(D) and the gate electrode 14 on the n-typehigh-concentration drain region 14 _(D).

After selectively removing the unreacted cobalt film, a second heattreatment is performed to thereby stabilize structures of the silicidefilms 5 _(G), 5 _(S), and 5 _(D). The protection film is then removed.

After forming the interlayer insulating film 9 on the substrate 1, aplurality of contact holes are formed in the interlayer insulating film9, and a conductive material is buried into each contact hole, therebyforming the drain contact 10 _(D1), 10 _(D2), 10 _(D3), and the sourcecontacts 10 _(S1), 10 _(S2), and 10 _(S3). Next, after forming the metalwirings 11 _(D) and 11 _(S) connected to the drain contacts 10 _(D1), 10_(D2), and 10 _(D3), and to the source contacts 10 _(S1), 10 _(S2), and10 _(S3) on the interlayer insulating film 9, respectively, theinterlayer insulating film 12 is formed. The semiconductor deviceaccording to this embodiment can be thereby obtained.

Alternatively, the protection film for preventing the silicide film frombeing formed on the region 13 _(D) may be left without removing it. Ifso, with the structure shown in FIGS. 7, 8B, and 8C, the protection filmremains present between the n-type high-concentration drain region 14_(D) and the interlayer insulating film 9 in the region 13 _(D) which islocated on the n-type high-concentration drain region 14 _(D) and onwhich the silicide film is not formed.

Modification of Third Embodiment

A modification of the third embodiment will be described with referenceto FIG. 9. FIG. 9 is a plan view which depicts a modification of theelectrostatic discharge protected transistor according to the thirdembodiment of the present invention. In FIG. 9, the same referencenumerals denote the same constituent elements as those in the thirdembodiment shown in FIG. 7.

In this modification, regions 13 _(S) in which the silicide film is notformed are provided in part of regions located between respective pairsof the source contacts 10 _(S1) to 10 _(S3) on the n-typehigh-concentration source region 14 _(S). In addition, an on-sourcesilicide film 5 _(SX) smaller in width in the gate length direction thanthe on-source silicide film 5 _(SX) in other regions is formed inportions located between the regions 13 _(S) in which the silicide filmis not formed and the sidewall spacers 7 formed on the side surfaces ofthe gate electrode 4 on the n-type high-concentration source region 14_(S). The other constituent elements are equal to those shown in FIG. 7.

With this configuration, the same advantages as those of the thirdembodiment can be attained. In addition, since the high-resistance andsmall-width on-source silicide film 5 _(SX) is provided between therespective pairs of the transistors 21 to 23, it is possible to furtherensure preventing the local current concentration. Namely, since theregions between the respective pairs of the adjacent drains and theregions between the respective pairs of the adjacent sources have highresistances, it is possible to prevent a current from flowing betweenthe adjacent transistors, i.e., prevent a current flowing between thedrain contact 10 _(D1) and the source contact 10 _(S1) from flowingbetween the drain contact 10 _(D2) and the source contact 10 _(S2). As aconsequence and because of the fact that the transistors 21 to 23 arenot isolated from one another by the element isolation regions, it ispossible to prevent the local current concentration without causing anincrease in the area of the semiconductor device.

In the embodiments and the modifications of the embodiments, the nchannel transistors have been described. However, the present inventionis similarly applicable to p channel transistors. If so, it is possibleto prevent the local current concentration without causing an increasein the area.

1. A semiconductor device, comprising: a semiconductor substrate whichincludes an active region; an element isolation region provided in aregion surrounding sides of said active region of said semiconductorsubstrate; a gate insulating film provided on said active region; a gateelectrode provided on said gate insulating film; a source region and adrain region which are provided in regions located below sides of saidgate electrode in said active region, respectively; an on-sourcesilicide film provided on said source region; an on-drain silicide filmprovided on said drain region; a plurality of source contacts which areprovided over said source region with said on-source silicide filminterposed therebetween, and which are aligned in a gate widthdirection; and a plurality of drain contacts which are provided oversaid drain region with said on-drain silicide film interposedtherebetween, and which are aligned in the gate width direction, whereinsaid on-drain silicide film is provided to be divided into a pluralityof on-drain silicide films and the resultant on-drain silicide films areisolated from one another in at least one region out of regions locatedbetween respective adjacent pairs of the drain contacts among saidplurality of drain contacts.
 2. The semiconductor device of claim 1,wherein said on-drain silicide film is provided to be divided into theplurality of on-drain silicide films and the resultant on-drain silicidefilms are isolated to correspond to said drain contacts, respectively.3. The semiconductor device of claim 1, wherein said on-source silicidefilm is provided on an entire surface of said source region.
 4. Thesemiconductor device of claim 1, wherein said on-source silicide film isprovided to be divided into a plurality of on-source silicide films andthe resultant on-source silicide films are isolated from one another inat least one region out of regions located between respective adjacentpairs of the source contacts among said plurality of source contacts. 5.The semiconductor device of claim 1, wherein a protection film isprovided on said drain region in at least one region out of regions putbetween the respective adjacent pairs of the drain contacts among saidplurality of drain contacts, thereby providing said on-drain silicidefilms to be isolated from one another.
 6. The semiconductor device ofclaim 1, wherein said gate electrode is composed of a polysilicon film,and an on-gate silicide film is formed on said gate electrode. 7-15.(canceled)